A typical Context Adaptive binary arithmetic coding (CABAC) decoder reads and updates state information for each decoded bit. The state information is often stored in a memory unit. In a data sequence, for each decoded bit, state information is read from the memory, an arithmetic operation is performed, and updated state information is written back to the memory. In a synchronous system, these operations are typically allocated to multiple clock cycles, forming a pipeline, if the entire sequence cannot be completed in one clock cycle.
Each of the needed operations takes a different amount of time to complete. Therefore, the clock rate is limited by the slowest stage of the pipeline. In other stages there will typically be slack time to the extent that the full cycle time is not needed to complete the operation(s) in that stage. As a result, the total time to decode one bit, which is determined by the number of pipeline stages times the clock cycles time, may be significantly longer than the sum of the times needed to complete each individual operation.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.